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Message-ID: <1395842272-15267-9-git-send-email-kishon@ti.com>
Date: Wed, 26 Mar 2014 19:27:48 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: <devicetree@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-omap@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<bhelgaas@...gle.com>, <mohit.kumar@...com>, <jg1.han@...sung.com>
CC: <robh+dt@...nel.org>, <pawel.moll@....com>, <mark.rutland@....com>,
<ijc+devicetree@...lion.org.uk>, <galak@...eaurora.org>,
<rob@...dley.net>, <linux@....linux.org.uk>, <tony@...mide.com>,
<rnayak@...com>, <paul@...an.com>, <kishon@...com>
Subject: [RFC PATCH 08/12] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 9e0bb09..5f13189 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = <0x021c>, <0x0220>;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@...093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@...0821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
--
1.7.9.5
--
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