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Date: Fri, 4 Apr 2014 11:05:32 +0100
From: Mark Brown <broonie@...nel.org>
To: Nicolin Chen <Guangyu.Chen@...escale.com>
Cc: Li.Xiubo@...escale.com, linux-kernel@...r.kernel.org,
linuxppc-dev@...ts.ozlabs.org, alsa-devel@...a-project.org,
timur@...i.org
Subject: Re: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
> The BCP bit in TCR4/RCR4 register rules as followings:
> 0 Bit clock is active high with drive outputs on rising edge
> and sample inputs on falling edge.
> 1 Bit clock is active low with drive outputs on falling edge
> and sample inputs on rising edge.
Applied, thanks.
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