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Message-ID: <20140408110738.GA10745@MrMyself>
Date:	Tue, 8 Apr 2014 19:07:40 +0800
From:	Nicolin Chen <Guangyu.Chen@...escale.com>
To:	Mark Brown <broonie@...nel.org>
CC:	<linux-kernel@...r.kernel.org>, <linuxppc-dev@...ts.ozlabs.org>,
	<alsa-devel@...a-project.org>
Subject: Re: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations

On Fri, Apr 04, 2014 at 11:05:32AM +0100, Mark Brown wrote:
> On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
> > The BCP bit in TCR4/RCR4 register rules as followings:
> >   0 Bit clock is active high with drive outputs on rising edge
> >     and sample inputs on falling edge.
> >   1 Bit clock is active low with drive outputs on falling edge
> >     and sample inputs on rising edge.
> 
> Applied, thanks.

Sir, I can't find this patch on any of the remote branches: for-next,
topic/fsl-sai and fix/fsl-sai. Where could I find it?

Thank you,
Nicolin

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