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Message-ID: <20140421102750.GA27209@amd.pavel.ucw.cz>
Date:	Mon, 21 Apr 2014 12:27:50 +0200
From:	Pavel Machek <pavel@....cz>
To:	tthayer@...era.com
Cc:	robherring2@...il.com, pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org, galak@...eaurora.org, rob@...dley.net,
	linux@....linux.org.uk, dinguyen@...era.com,
	dougthompson@...ssion.com, grant.likely@...aro.org,
	tthayer.linux@...il.com, Borislav Petkov <bp@...en8.de>,
	devicetree@...r.kernel.org, linux-edac@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for
 CycloneV/ArriaV

Hi!

> From: Thor Thayer <tthayer@...era.com>
> 
> Added EDAC support for reporting ECC errors of CycloneV
> and ArriaV SDRAM controller.
> - The SDRAM Controller registers are used by the FPGA bridge so
>   these are accessed through the syscon interface.
> - The configuration of the SDRAM memory size for the EDAC framework
>   is discovered from the SDRAM Controller registers.
> - Documentation of the bindings in devicetree/bindings/arm/altera/
>   socfpga-sdram-edac.txt
> - Correction of single bit errors, detection of double bit errors.
> 
> ---
> v2: Use the SDRAM controller registers to calculate memory size
>     instead of the Device Tree. Update To & Cc list. Add maintainer 
>     information.

I'd reduce number of *s in the messages, otherwise

Reviewed-by: Pavel Machek <pavel@....cz>

for whole series.
								Pavel

-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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