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Message-ID: <20140525190211.GT10768@lukather>
Date: Sun, 25 May 2014 21:02:11 +0200
From: Maxime Ripard <maxime.ripard@...e-electrons.com>
To: Chen-Yu Tsai <wens@...e.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Samuel Ortiz <sameo@...ux.intel.com>,
Lee Jones <lee.jones@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Mike Turquette <mturquette@...aro.org>,
Emilio Lopez <emilio@...pez.com.ar>,
Linus Walleij <linus.walleij@...aro.org>,
linux-serial@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Hans de Goede <hdegoede@...hat.com>,
Boris BREZILLON <boris.brezillon@...e-electrons.com>,
Luc Verhaegen <libv@...net.be>
Subject: Re: [PATCH 10/22] clk: sunxi: Add support for PLL6 pre-divider on
AHB1 clock
On Fri, May 23, 2014 at 03:51:13PM +0800, Chen-Yu Tsai wrote:
> On the A31 and A23, the PLL6 input to the AHB1 clock has a 2 bit wide
> pre-divider. This was verified from the A23 user manual and A31/A23 SDK
> sources.
>
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>
No, it should be part of the AHB1 clock code itself. It's internal
clock logic, isn't a clock per se, and as such, shouldn't be
reprensented as a separate clock.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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