linux-kernel - Re: Questions About a Semi-Soft irqchip Device

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20140708145639.GD13433@titan.lakedaemon.net>
Date:	Tue, 8 Jul 2014 10:56:39 -0400
From:	Jason Cooper <jason@...edaemon.net>
To:	Jon Loeliger <loeliger@...il.com>
Cc:	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
	Thomas Gleixner <tglx@...utronix.de>,
	Rob Herring <robh+dt@...nel.org>,
	Grant Likely <grant.likely@...aro.org>
Subject: Re: Questions About a Semi-Soft irqchip Device

Jon,

On Tue, Jul 08, 2014 at 09:02:14AM -0500, Jon Loeliger wrote:
> My IP block provides software-assignable interrupts.  That
> is, I have a large pool of interrupt sources, and a large pool
> of interrupt bits in the controller, but they are not physically
> tied together. Instead they are assigned by some driver as it
> initializes and allocates resources.  This, I think, means that
> I can not describe the interrupt  bindings in the DTS file.

Please take a look at the crossbar driver.  It's had quite a bit of
cleanup this cycle, so you may way to look at

  git://git.infradead.org/users/jcooper/linux.git irqchip/crossbar

It sounds very similar.

thx,

Jason.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/