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Message-ID: <53BFFEAD.7000405@nvidia.com>
Date:	Fri, 11 Jul 2014 18:11:41 +0300
From:	Tuomas Tynkkynen <ttynkkynen@...dia.com>
To:	Thierry Reding <thierry.reding@...il.com>,
	Peter De Schrijver <pdeschrijver@...dia.com>
CC:	Viresh Kumar <viresh.kumar@...aro.org>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Prashant Gaikwad <pgaikwad@...dia.com>,
	Mike Turquette <mturquette@...aro.org>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH 12/13] cpufreq: Add cpufreq driver for Tegra124

On 11/07/14 17:57, Thierry Reding wrote:

>> I don't think that's going to work? The voltage scaling is handled in hw.
>
> Do we have to handle it in hardware or can we opt to do it in software,
> too?
>

With the PLLX, voltage scaling is done entirely in SW. With the DFLL,
it's possible to stay in open-loop mode and do it in SW, but there's
not much point in that.

-- 
nvpublic
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