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Message-ID: <1405334543-25509-4-git-send-email-kishon@ti.com>
Date: Mon, 14 Jul 2014 16:12:18 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: <linux-kernel@...r.kernel.org>, <tony@...mide.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-omap@...r.kernel.org>
CC: <kishon@...com>, Rajendra Nayak <rnayak@...com>,
Tero Kristo <t-kristo@...com>, Paul Walmsley <paul@...an.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Kumar Gala <galak@...eaurora.org>
Subject: [RESEND PATCH 3/8] ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.
Cc: Rajendra Nayak <rnayak@...com>
Cc: Tero Kristo <t-kristo@...com>
Cc: Paul Walmsley <paul@...an.com>
Cc: Tony Lindgren <tony@...mide.com>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Pawel Moll <pawel.moll@....com>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Kumar Gala <galak@...eaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index f5dca1f..3ff6d7c 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,6 +1165,14 @@
reg = <0x021c>, <0x0220>;
};
+ optfclk_pciephy_32khz: optfclk_pciephy_32khz@...093b0 {
+ compatible = "ti,gate-clock";
+ clocks = <&sys_32k_ck>;
+ #clock-cells = <0>;
+ reg = <0x13b0>;
+ ti,bit-shift = <8>;
+ };
+
optfclk_pciephy_div: optfclk_pciephy_div@...0821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
--
1.7.9.5
--
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