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Date:	Mon, 14 Jul 2014 16:12:19 +0530
From:	Kishon Vijay Abraham I <kishon@...com>
To:	<linux-kernel@...r.kernel.org>, <tony@...mide.com>,
	<devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-omap@...r.kernel.org>
CC:	<kishon@...com>, Rajendra Nayak <rnayak@...com>,
	Tero Kristo <t-kristo@...com>, Paul Walmsley <paul@...an.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Kumar Gala <galak@...eaurora.org>, Keerthy <j-keerthy@...com>
Subject: [RESEND PATCH 4/8] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance

There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.

Cc: Rajendra Nayak <rnayak@...com>
Cc: Tero Kristo <t-kristo@...com>
Cc: Paul Walmsley <paul@...an.com>
Cc: Tony Lindgren <tony@...mide.com>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Pawel Moll <pawel.moll@....com>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Kumar Gala <galak@...eaurora.org>
Signed-off-by: Keerthy <j-keerthy@...com>
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 3ff6d7c..fe5db55 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1165,7 +1165,7 @@
 		reg = <0x021c>, <0x0220>;
 	};
 
-	optfclk_pciephy_32khz: optfclk_pciephy_32khz@...093b0 {
+	optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@...093b0 {
 		compatible = "ti,gate-clock";
 		clocks = <&sys_32k_ck>;
 		#clock-cells = <0>;
@@ -1183,7 +1183,7 @@
 		ti,max-div = <2>;
 	};
 
-	optfclk_pciephy_clk: optfclk_pciephy_clk@...093b0 {
+	optfclk_pciephy1_clk: optfclk_pciephy1_clk@...093b0 {
 		compatible = "ti,gate-clock";
 		clocks = <&apll_pcie_ck>;
 		#clock-cells = <0>;
@@ -1191,7 +1191,7 @@
 		ti,bit-shift = <9>;
 	};
 
-	optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@...093b0 {
+	optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@...093b0 {
 		compatible = "ti,gate-clock";
 		clocks = <&optfclk_pciephy_div>;
 		#clock-cells = <0>;
-- 
1.7.9.5

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