lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CALCETrVfqBpJaTJCnDH8pZf4-6x6oojv+8Vvm3XudJfhbstdOQ@mail.gmail.com>
Date:	Tue, 15 Jul 2014 12:53:30 -0700
From:	Andy Lutomirski <luto@...capital.net>
To:	Toshi Kani <toshi.kani@...com>
Cc:	"H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Arnd Bergmann <arnd@...db.de>,
	Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
	plagnioj@...osoft.com, tomi.valkeinen@...com,
	"linux-mm@...ck.org" <linux-mm@...ck.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Stefan Bader <stefan.bader@...onical.com>,
	Dave Airlie <airlied@...il.com>, Borislav Petkov <bp@...en8.de>
Subject: Re: [RFC PATCH 0/11] Support Write-Through mapping on x86

On Tue, Jul 15, 2014 at 12:34 PM, Toshi Kani <toshi.kani@...com> wrote:
> This RFC patchset is aimed to seek comments/suggestions for the design
> and changes to support of Write-Through (WT) mapping.  The study below
> shows that using WT mapping may be useful for non-volatile memory.
>
>   http://www.hpl.hp.com/techreports/2012/HPL-2012-236.pdf
>
> There were idea & patches to support WT in the past, which stimulated
> very valuable discussions on this topic.
>
>   https://lkml.org/lkml/2013/4/24/424
>   https://lkml.org/lkml/2013/10/27/70
>   https://lkml.org/lkml/2013/11/3/72
>
> This RFC patchset tries to address the issues raised by taking the
> following design approach:
>
>  - Keep the MTRR interface
>  - Keep the WB, WC, and UC- slots in the PAT MSR
>  - Keep the PAT bit unused
>  - Reassign the UC slot to WT in the PAT MSR
>
> There are 4 usable slots in the PAT MSR, which are currently assigned to:
>
>   PA0/4: WB, PA1/5: WC, PA2/6: UC-, PA3/7: UC
>
> The PAT bit is unused since it shares the same bit as the PSE bit and
> there was a bug in older processors.  Among the 4 slots, the uncached
> memory type consumes 2 slots, UC- and UC.  They are functionally
> equivalent, but UC- allows MTRRs to overwrite it with WC.  All interfaces
> that set the uncached memory type use UC- in order to work with MTRRs.
> The PA3/7 slot is effectively unused today.  Therefore, this patchset
> reassigns the PA3/7 slot to WT.  If MTRRs get deprecated in future,
> UC- can be reassigned to UC, and there is still no need to consume
> 2 slots for the uncached memory type.

Note that MTRRs are already partially deprecated: all drivers *should*
be using arch_phys_wc_add, not mtrr_add, and arch_phys_wc_add is a
no-op on systems with working PAT.

Unfortunately, I never finished excising mtrr_add.  Finishing the job
wouldn't be very hard.

--Andy
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ