linux-kernel - [PATCH v5 3/4] ARM: dts: sirf: fix the pwm-cells and clocks

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Message-ID: <1405475714-10006-4-git-send-email-huayi.li@csr.com>
Date:	Wed, 16 Jul 2014 09:55:13 +0800
From:	Huayi Li <huayi.li@....com>
To:	Thierry Reding <thierry.reding@...il.com>,
	<linux-pwm@...r.kernel.org>,
	Grant Likely <grant.likely@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
CC:	<linux-arm-kernel@...ts.infradead.org>, <workgroup.linux@....com>,
	<rongjun.ying@....com>, <barry.song@....com>,
	Huayi Li <huayi.li@....com>
Subject: [PATCH v5 3/4] ARM: dts: sirf: fix the pwm-cells and clocks

This patch adds missed pwm-cells, clock-names and signal source
clock for PWM module.

Signed-off-by: Huayi Li <huayi.li@....com>
---
 arch/arm/boot/dts/atlas6.dtsi | 8 ++++++--
 arch/arm/boot/dts/prima2.dtsi | 8 ++++++--
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index bb22842..d424a69 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -638,10 +638,14 @@
                                 };
 			};
 
-			pwm@...30000 {
+			pwm: pwm@...30000 {
 				compatible = "sirf,prima2-pwm";
+				#pwm-cells = <2>;
 				reg = <0xb0130000 0x10000>;
-				clocks = <&clks 21>;
+				clocks = <&clks 21>, <&clks 1>, <&clks 2>,
+					<&clks 3>, <&clks 0>, <&clks 4>;
+				clock-names = "pwmc", "sigsrc0", "sigsrc1",
+					"sigsrc2", "sigsrc3", "sigsrc4";
 			};
 
 			efusesys@...40000 {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 963b7e5..68bb0c4 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -646,10 +646,14 @@
                                 };
 			};
 
-			pwm@...30000 {
+			pwm: pwm@...30000 {
 				compatible = "sirf,prima2-pwm";
+				#pwm-cells = <2>;
 				reg = <0xb0130000 0x10000>;
-				clocks = <&clks 21>;
+				clocks = <&clks 21>, <&clks 1>, <&clks 2>,
+					<&clks 3>, <&clks 0>, <&clks 4>;
+				clock-names = "pwmc", "sigsrc0", "sigsrc1",
+					"sigsrc2", "sigsrc3", "sigsrc4";
 			};
 
 			efusesys@...40000 {
-- 
1.9.3



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