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Date:	Fri, 18 Jul 2014 17:52:12 -0700
From:	Andi Kleen <andi@...stfloor.org>
To:	peterz@...radead.org
Cc:	eranian@...gle.com, linux-kernel@...r.kernel.org,
	Andi Kleen <ak@...ux.intel.com>
Subject: [PATCH 3/3] perf, x86: Fix haswell mem hierarchy flags reporting

From: Andi Kleen <ak@...ux.intel.com>

This fixes a bug introduced with

commit 722e76e60f2775c21b087ff12c5e678cf0ebcaaf
Author: Stephane Eranian <eranian@...gle.com>
Date:   Thu May 15 17:56:44 2014 +0200

    fix Haswell precise store data source encoding

When returning early we need to return the complete value of the
memory hierarchy, not just the mem_lvl. Otherwise any load/store/na
flags set early get lost.

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel_ds.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index cafb24f..7f7b117 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -121,7 +121,6 @@ static u64 precise_store_data_hsw(struct perf_event *event, u64 status,
 		dse.mem_op = PERF_MEM_OP_STORE;
 	else
 		dse.mem_op = PERF_MEM_OP_NA;
-	dse.mem_lvl = PERF_MEM_LVL_NA;
 
 	/*
 	 * L1 info only valid for following events:
@@ -131,8 +130,10 @@ static u64 precise_store_data_hsw(struct perf_event *event, u64 status,
 	 * MEM_UOPS_RETIRED.SPLIT_STORES
 	 * MEM_UOPS_RETIRED.ALL_STORES
 	 */
-	if (cfg != 0x12d0 && cfg != 0x22d0 && cfg != 0x42d0 && cfg != 0x82d0)
-		return dse.mem_lvl;
+	if (cfg != 0x12d0 && cfg != 0x22d0 && cfg != 0x42d0 && cfg != 0x82d0) {
+		dse.mem_lvl = PERF_MEM_LVL_NA;
+		return dse.val;
+	}
 
 	if (status & 1)
 		dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
-- 
1.9.3

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