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Date:	Mon, 11 Aug 2014 21:58:11 +0200
From:	Stephane Eranian <eranian@...gle.com>
To:	Peter Zijlstra <peterz@...radead.org>
Cc:	LKML <linux-kernel@...r.kernel.org>,
	"mingo@...e.hu" <mingo@...e.hu>,
	"ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: Re: [PATCH v2 0/4] perf/x86: simplify PEBS event constraint management

On Mon, Aug 11, 2014 at 9:56 PM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Mon, Aug 11, 2014 at 09:27:09PM +0200, Stephane Eranian wrote:
>> This patchkit revamps the PEBS tables on most Intel CPUs, both simplifying
>> and fixing a couple of problems on Haswell processors:
>>  - All PEBS event supported
>>  - data address and data source is now reported correctly for all events
>>
>> We simplify the tables by using the fact that non-PEBS event when used
>> in PEBS mode do not generate any PEBS records , thus they are safe to use.
>> This helps simplify the PEBS event constraints because they do not need
>> to list all suported PEBS events anymore. They only need to list
>> the special PEBS events, such as precise store and load latency.
>> This avoid some issues where the kernel is missing some PEBS events.
>>
>> In V2, we cleanup some more the precise_datala() for store events.
>
> Ah, I just queued your v1, time to swap patches around I suppose :-)

Yeah, I cleanup some more based on more comments from Andi.
No more hardcoded event codes.
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