lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Fri, 19 Sep 2014 17:39:32 +0100
From:	Russell King - ARM Linux <linux@....linux.org.uk>
To:	Alexandre Belloni <alexandre.belloni@...e-electrons.com>
Cc:	Tomasz Figa <t.figa@...sung.com>,
	linux-samsung-soc@...r.kernel.org,
	Kukjin Kim <kgene.kim@...sung.com>, lauraa@...eaurora.org,
	tony@...mide.com, linus.walleij@...aro.org,
	linux-kernel@...r.kernel.org, drake@...lessm.com,
	loeliger@...il.com, santosh.shilimkar@...com,
	linux-omap@...r.kernel.org, Tomasz Figa <tomasz.figa@...il.com>,
	linux-arm-kernel@...ts.infradead.org,
	Marek Szyprowski <m.szyprowski@...sung.com>
Subject: Re: [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch
	settings

On Fri, Sep 19, 2014 at 11:50:01AM +0200, Alexandre Belloni wrote:
> On 26/08/2014 at 16:17:57 +0200, Tomasz Figa wrote :
> > Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
> > settings configured in registers leading to crashes if L2C is enabled
> > without overriding them. This patch introduces bindings to enable
> > prefetch settings to be specified from DT and necessary support in the
> > driver.
> > 
> > Signed-off-by: Tomasz Figa <t.figa@...sung.com>
> 
> Tested-by: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
> 
> It is working and useful on Atmel's sama5d4 were the bootloader is not
> configuring the L2C prefetch. However, I'm wondering whether we should
> add support for setting L310_PREFETCH_CTRL_DATA_PREFETCH and
> L310_PREFETCH_CTRL_INSTR_PREFETCH. I'm currently doing it by using
> ".l2c_aux_val    = L310_AUX_CTRL_DATA_PREFETCH |
> L310_AUX_CTRL_INSTR_PREFETCH" (those are the same bits) but this has the
> disadvantage of displaying the "L2C: platform modifies aux control
> register:" twice.

The L2C documentation, freely available from the ARM infocentre website,
has the answer to this for you.

The two bits in the prefetch control register which control the data
and instruction prefetching are aliases of the aux control register.
If you set them to a value in one register, they are reflected in the
other.

The reason for that is that once the L2 cache is enabled, writes to
the aux control register are no longer permitted, but it's safe to
enable and disable the prefetching with the cache already enabled.
This reason is even stated in the documentation.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists