linux-kernel - Re: bit fields && data tearing

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Message-ID: <20140925161212.GA27218@xo-6d-61-c0.localdomain>
Date:	Thu, 25 Sep 2014 18:12:12 +0200
From:	Pavel Machek <pavel@....cz>
To:	Peter Hurley <peter@...leysoftware.com>
Cc:	David Laight <David.Laight@...LAB.COM>,
	"'paulmck@...ux.vnet.ibm.com'" <paulmck@...ux.vnet.ibm.com>,
	Jakub Jelinek <jakub@...hat.com>,
	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>,
	"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
	"linux-ia64@...r.kernel.org" <linux-ia64@...r.kernel.org>,
	Mikael Pettersson <mikpelinux@...il.com>,
	Oleg Nesterov <oleg@...hat.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	James Bottomley <James.Bottomley@...senPartnership.com>,
	Tony Luck <tony.luck@...el.com>,
	Paul Mackerras <paulus@...ba.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
	Miroslav Franc <mfranc@...hat.com>,
	Richard Henderson <rth@...ddle.net>,
	"linux-arm@...r.kernel.org" <linux-arm@...r.kernel.org>
Subject: Re: bit fields && data tearing

On Fri 2014-09-05 12:17:16, Peter Hurley wrote:
> On 09/05/2014 08:37 AM, David Laight wrote:
> > From: Peter Hurley
> >> On 09/05/2014 04:30 AM, David Laight wrote:
> >>> I've seen gcc generate 32bit accesses for 16bit structure members on arm.
> >>> It does this because of the more limited range of the offsets for the 16bit access.
> >>> OTOH I don't know if it ever did this for writes - so it may be moot.
> >>
> >> Can you recall the particulars, like what ARM config or what code?
> >>
> >> I tried an overly-simple test to see if gcc would bump up to the word load for
> >> the 12-bit offset mode, but it stuck with register offset rather than immediate
> >> offset. [I used the compiler options for allmodconfig and a 4.8 cross-compiler.]
> >>
> >> Maybe the test doesn't generate enough register pressure on the compiler?
> > 
> > Dunno, I would have been using a much older version of the compiler.
> > It is possible that it doesn't do it any more.
> > It might only have done it for loads.
> > 
> > The compiler used to use misaligned 32bit loads for structure
> > members on large 4n+2 byte boundaries as well.
> > I'm pretty sure it doesn't do that either.
> > 
> > There have been a lot of compiler versions since I was compiling
> > anything for arm.
> 
> Yeah, it seems gcc for ARM no longer uses the larger operand size as a
> substitute for 12-bit immediate offset addressing mode, even for reads.
> 
> While this test:
> 
> struct x {
> 	short b[12];
> };
> 
> short load_b(struct x *p) {
> 	return p->b[8];
> }
> 
> generates the 8-bit immediate offset form,
> 
> short load_b(struct x *p) {
>    0:	e1d001f0 	ldrsh	r0, [r0, #16]
>    4:	e12fff1e 	bx	lr
> 
> 
> pushing the offset out past 256:
> 
> struct x {
> 	long unused[64];
> 	short b[12];
> };
> 
> short load_b(struct x *p) {
> 	return p->b[8];
> }
> 
> generates the register offset addressing mode instead of 12-bit immediate:
> 
> short load_b(struct x *p) {
>    0:	e3a03e11 	mov	r3, #272	; 0x110
>    4:	e19000f3 	ldrsh	r0, [r0, r3]
>    8:	e12fff1e 	bx	lr

If we rely on new gcc features for correctness, does minimum compiler version need to be updated?
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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