linux-kernel - Re: [PATCH v5 09/10] ARM: dts: berlin: add the Ethernet node

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Message-ID: <54296DDA.8000400@gmail.com>
Date:	Mon, 29 Sep 2014 16:34:02 +0200
From:	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
To:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>,
	Antoine Tenart <antoine.tenart@...e-electrons.com>
CC:	thomas.petazzoni@...e-electrons.com, zmxu@...vell.com,
	devicetree@...r.kernel.org, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org, alexandre.belloni@...e-electrons.com,
	jszhang@...vell.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v5 09/10] ARM: dts: berlin: add the Ethernet node

On 09/26/2014 07:25 PM, Sergei Shtylyov wrote:
> On 09/26/2014 06:33 PM, Antoine Tenart wrote:
>> This patch adds the Ethernet node, enabling the network unit on Berlin
>> BG2Q SoCs.
>
>> Signed-off-by: Antoine Tenart <antoine.tenart@...e-electrons.com>
>> Acked-by: Arnd Bergmann <arnd@...db.de>
>> ---
>>   arch/arm/boot/dts/berlin2q.dtsi | 17 +++++++++++++++++
>>   1 file changed, 17 insertions(+)
>
>> diff --git a/arch/arm/boot/dts/berlin2q.dtsi
>> b/arch/arm/boot/dts/berlin2q.dtsi
>> index 902eddb19cd8..d442b22fd1ea 100644
>> --- a/arch/arm/boot/dts/berlin2q.dtsi
>> +++ b/arch/arm/boot/dts/berlin2q.dtsi
>> @@ -114,6 +114,23 @@
>>               #interrupt-cells = <3>;
>>           };
>>
>> +        eth0: ethernet@...000 {
>> +            compatible = "marvell,pxa168-eth";
>> +            reg = <0xb90000 0x10000>;
>> +            clocks = <&chip CLKID_GETH0>;
>> +            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>> +            /* set by bootloader */
>> +            local-mac-address = [00 00 00 00 00 00];
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +            phy-handle = <&ethphy0>;
>> +            status = "disabled";
>> +
>> +            ethphy0: ethernet-phy@0 {
>> +                reg = <0>;
>> +            };
>> +        };
>> +
>
>     Hm, is the PHY internal to the Ethernet controller?

Sergei,

at least for BG2 and BG2CD the PHY is internal to the SoC. Also,
MDIO bus is part of the ethernet IP, so placing the PHY inside
the combined Ethernet/MDIO IP node is sane.

Sebastian
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