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Message-ID: <20141001154523.GF18271@pd.tnic>
Date: Wed, 1 Oct 2014 17:45:24 +0200
From: Borislav Petkov <bp@...en8.de>
To: Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
Cc: bhelgaas@...gle.com, linux-pci@...r.kernel.org, tglx@...utronix.de,
hpa@...or.com, x86@...nel.org, bp@...e.de,
dan.carpenter@...cle.com, dougthompson@...ssion.com,
m.chehab@...sung.com, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 4/4] edac, amd64_edac: Add F15h M60h support
On Wed, Oct 01, 2014 at 10:32:58AM -0500, Aravind Gopalakrishnan wrote:
> >>+ if (dcsm & 0x3) {
> >>+ /* LRDIMMs */
> >>+ edac_dbg(1, " DIMM type: LRDIMM %dx rank multiply;"
> >>+ "CS = %d; all DIMMs support ECC: %s\n",
> >>+ (dcsm & 0x3), cs,
> >>+ (dclr & BIT(19)) ? "yes" : "no");
> >Why do we need to iterate over the DRAM CS sets? Just for the rank
> >multiplier, apparently. We dump those normally in read_dct_base_mask(),
> >though.
>
> It's not just for rank multiplier.. we find that it's LRDIMM only by
> examining dcsm. Hence the iteration here..
So we can look only at the first DCSM, no? Or are there systems with
different types of LRDIMMs on one DCT?
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
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