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Date:	Tue, 14 Oct 2014 15:46:09 +0200
From:	Thierry Reding <thierry.reding@...il.com>
To:	Mikko Perttunen <mikko.perttunen@...si.fi>
Cc:	Mark Rutland <mark.rutland@....com>,
	Tomeu Vizoso <tomeu.vizoso@...labora.com>,
	Stephen Warren <swarren@...dia.com>,
	Rhyland Klein <rklein@...dia.com>,
	Thierry Reding <treding@...dia.com>,
	Javier Martinez Canillas <javier.martinez@...labora.co.uk>,
	Mikko Perttunen <mperttunen@...dia.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <Pawel.Moll@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Stephen Warren <swarren@...dotorg.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 04/10] of: Add Tegra124 EMC bindings

On Tue, Oct 14, 2014 at 04:36:45PM +0300, Mikko Perttunen wrote:
> On 10/10/2014 04:14 PM, Mark Rutland wrote:
> >On Fri, Oct 10, 2014 at 01:46:55PM +0100, Tomeu Vizoso wrote:
> >>From: Mikko Perttunen <mperttunen@...dia.com>
> >>
> >>Add binding documentation for the nvidia,tegra124-emc device tree node.
> >>
> >>Signed-off-by: Mikko Perttunen <mperttunen@...dia.com>
> >>Signed-off-by: Tomeu Vizoso <tomeu.vizoso@...labora.com>
> >>---
> >>  .../bindings/memory-controllers/tegra-emc.txt      | 41 ++++++++++++++++++++++
> >>  1 file changed, 41 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
> >>
> >>diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
> >>new file mode 100644
> >>index 0000000..6282c6b
> >>--- /dev/null
> >>+++ b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
> >>@@ -0,0 +1,41 @@
> >>+Tegra124 SoC EMC controller
> >>+
> >>+Required properties :
> >>+- compatible : "nvidia,tegra124-emc".
> >>+- reg : Should contain 1 entry:
> >>+  - EMC register set
> >>+
> >>+The node should contain a "timings@i" subnode for each supported RAM type
> >>+  (see field RAM_CODE in register PMC_STRAPPING_OPT_A)
> >>+Required properties for "timings@i" nodes :
> >>+- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
> >>+  is used for.
> >>+
> >>+Each "timings@i" node should contain "timing@j" subnodes. One "timing@j"
> >>+  node should exist for each supported EMC clock rate.
> >
> >What do the i and j correspond to?
> 
> Arbitrary integers, preferably starting from 0 and increasing, similar as
> with regulator@i etc. Each set of `j's is independent. (Actually, these
> values are never used anywhere for anything).

Perhaps they should be used, then? Typically the unit-address matches
the (first) value of the reg property. Perhaps in this case it would
make sense to make it match the value in clock-frequency for j, and i
could correspond to the value of the nvidia,ram-code property.

Thierry

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