linux-kernel - Re: [PATCH v5 12/20] x86: perf: intel

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Date:	Wed, 22 Oct 2014 16:45:43 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	Robert Richter <rric@...nel.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Mike Galbraith <efault@....de>,
	Paul Mackerras <paulus@...ba.org>,
	Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <ak@...ux.intel.com>, kan.liang@...el.com,
	adrian.hunter@...el.com, acme@...radead.org
Subject: Re: [PATCH v5 12/20] x86: perf: intel_pt: Intel PT PMU driver

On Mon, Oct 13, 2014 at 04:45:40PM +0300, Alexander Shishkin wrote:
> +static int pt_config(struct perf_event *event)
> +{
> +	u64 reg;
> +
> +	reg = RTIT_CTL_TOPA | RTIT_CTL_BRANCH_EN;
> +
> +	if (!event->attr.exclude_kernel)
> +		reg |= RTIT_CTL_OS;
> +	if (!event->attr.exclude_user)
> +		reg |= RTIT_CTL_USR;
> +
> +	reg |= (event->attr.config & PT_CONFIG_MASK);
> +
> +	/*
> +	 * User can try to set bits in RTIT_CTL through PT_BYPASS_MASK,
> +	 * that aren't supported by the hardware. Weather or not a
> +	 * particular bitmask is supported by a cpu can't be determined
> +	 * via cpuid or otherwise, so we have to rely on #GP handling
> +	 * to catch these cases.
> +	 */
> +	return wrmsrl_safe(MSR_IA32_RTIT_CTL, reg);
> +}

Whether the weather is nice or not :-)

But no, this cannot be, once we've accepted the event is must be
programmable. Failing at the time of programming is vile; pmu::start()
is a void return, failure is not an option there.

The fact that the hardware cannot even tell you the supported mask is
further fail.

IIRC I think Andi once suggested probing each of the 64 bits in that MSR
to determine the supported mask at device init time.

BTW, what's that RTIT thing? Did someone forget to propagate the latest
name change of the thing or so?
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