linux-kernel - Re: [PATCH v5 12/20] x86: perf: intel

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Date:	Wed, 22 Oct 2014 16:49:52 +0200
From:	Peter Zijlstra <peterz@...radead.org>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	Robert Richter <rric@...nel.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Mike Galbraith <efault@....de>,
	Paul Mackerras <paulus@...ba.org>,
	Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <ak@...ux.intel.com>, kan.liang@...el.com,
	adrian.hunter@...el.com, acme@...radead.org
Subject: Re: [PATCH v5 12/20] x86: perf: intel_pt: Intel PT PMU driver

On Mon, Oct 13, 2014 at 04:45:40PM +0300, Alexander Shishkin wrote:
> +static void pt_config_start(bool start)
> +{
> +	u64 ctl;
> +
> +	rdmsrl(MSR_IA32_RTIT_CTL, ctl);
> +	if (start)
> +		ctl |= RTIT_CTL_TRACEEN;
> +	else
> +		ctl &= ~RTIT_CTL_TRACEEN;
> +	wrmsrl(MSR_IA32_RTIT_CTL, ctl);
> +
> +	/*
> +	 * A wrmsr that disables trace generation serializes other PT
> +	 * registers and causes all data packets to be written to memory,
> +	 * but a fence is required for the data to become globally visible.
> +	 *
> +	 * The below WMB, separating data store and aux_head store matches
> +	 * the consumer's RMB that separates aux_head load and data load.
> +	 */
> +	if (!start)
> +		wmb();
> +}

wmb is sfence, is that sufficient? One would have expected an mfence
since that would also orders later reads.
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