linux-kernel - Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common clock framework

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Message-ID: <544A53E3.7040501@gmail.com>
Date:	Fri, 24 Oct 2014 15:28:03 +0200
From:	Tomasz Figa <tomasz.figa@...il.com>
To:	Daniel Drake <drake@...lessm.com>,
	Chanwoo Choi <cw00.choi@...sung.com>
CC:	linux-samsung-soc <linux-samsung-soc@...r.kernel.org>,
	Linux Kernel <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	Kukjin Kim <kgene.kim@...sung.com>, ben-linux@...ff.org,
	Russell King <linux@....linux.org.uk>,
	Mark Rutland <mark.rutland@....com>,
	Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
	Mike Turquette <mturquette@...aro.org>,
	thomas.abraham@...aro.org,
	Linus Walleij <linus.walleij@...aro.org>,
	Seung-Woo Kim <sw0312.kim@...sung.com>,
	Kyungmin Park <kyungmin.park@...sung.com>,
	InKi Dae <inki.dae@...sung.com>, geunsik.lim@...sung.com,
	jh80.chung@...sung.com, jaewon02.kim@...sung.com,
	ideal.song@...sung.com, yj44.cho@...sung.com,
	Sylwester Nawrocki <s.nawrocki@...sung.com>
Subject: Re: [PATCH 2/5] clk: samsung: exynos4415: Add clocks using common
 clock framework

On 24.10.2014 15:18, Daniel Drake wrote:
> On Sun, Oct 19, 2014 at 9:32 PM, Chanwoo Choi <cw00.choi@...sung.com> wrote:
>> This patch adds the new clock driver of Exynos4415 SoC based on Cortex-A9
>> using common clock framework. The CMU (Clock Management Unit) of Exynos4415
>> controls PLLs(Phase Locked Loops) and generates system clocks for CPU, buses
>> and function clocks for individual IPs.
> 
> There seems to be a lot in common here with other exynos4 variants in
> clk-exynos4.c. Have you considered just adding support for the 4415 in
> the existing driver?

I tried when I was still at Samsung and the outcome was far from being
nice. There are certain differences, such as separate address spaces of
few clock controllers and different bit fields in apparently similar
registers, which made resulting code quite ugly.

Also another advantage of separate driver is that it can be made without
duplicating initial fails of the driver for Exynos4, such as private
bindings for external clocks or clock controllers in different power
domains grouped together into one big logical clock controller, because
at development time they looked so (contiguous address space).

Best regards,
Tomasz
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