linux-kernel - Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella

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Message-ID: <eca8ae5de8184151b03d3fd8d23c62a7@BY2FFO11FD010.protection.gbl>
Date:	Fri, 7 Nov 2014 07:44:16 +0100
From:	Michal Simek <michal.simek@...inx.com>
To:	Andreas Färber <afaerber@...e.de>,
	Michal Simek <michal.simek@...inx.com>,
	Olof Johansson <olof@...om.net>, Arnd Bergmann <arnd@...db.de>
CC:	Sören Brinkmann <soren.brinkmann@...inx.com>,
	<linux-arm-kernel@...ts.infradead.org>,
	Andreas Olofsson <andreas@...pteva.com>,
	Matteo Vit <matteo.vit@...rwaredesign.com>,
	"Sean Rickerd" <srickerd@...e.com>, <stable@...r.kernel.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	"Kumar Gala" <galak@...eaurora.org>,
	Russell King <linux@....linux.org.uk>,
	"open list:OPEN FIRMWARE AND..." <devicetree@...r.kernel.org>,
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella

On 11/06/2014 06:22 PM, Andreas Färber wrote:
> The Parallella board comes with a U-Boot bootloader that loads one of
> two predefined FPGA bitstreams before booting the kernel. Both define an
> AXI interface to the on-board Epiphany processor.
> 
> Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
> 
> Otherwise accessing, e.g., the ESYSRESET register freezes the board,
> as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
> 
> Cc: <stable@...r.kernel.org> # 3.17.x
> Signed-off-by: Andreas Färber <afaerber@...e.de>
> ---
>  Michal/Olof, please consider this trivial patch as a fix for 3.18.

Acked-by: Michal Simek <michal.simek@...inx.com>

Olof, Arnd: Can you please pick this directly?

Thanks,
Michal

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