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Message-ID: <20141109005802.GE13855@quad.lixom.net>
Date: Sat, 8 Nov 2014 16:58:02 -0800
From: Olof Johansson <olof@...om.net>
To: Michal Simek <michal.simek@...inx.com>
Cc: Andreas Färber <afaerber@...e.de>,
Arnd Bergmann <arnd@...db.de>,
Sören Brinkmann <soren.brinkmann@...inx.com>,
linux-arm-kernel@...ts.infradead.org,
Andreas Olofsson <andreas@...pteva.com>,
Matteo Vit <matteo.vit@...rwaredesign.com>,
Sean Rickerd <srickerd@...e.com>, stable@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Russell King <linux@....linux.org.uk>,
"open list:OPEN FIRMWARE AND..." <devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
On Fri, Nov 07, 2014 at 07:44:16AM +0100, Michal Simek wrote:
> On 11/06/2014 06:22 PM, Andreas Färber wrote:
> > The Parallella board comes with a U-Boot bootloader that loads one of
> > two predefined FPGA bitstreams before booting the kernel. Both define an
> > AXI interface to the on-board Epiphany processor.
> >
> > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
> >
> > Otherwise accessing, e.g., the ESYSRESET register freezes the board,
> > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
> >
> > Cc: <stable@...r.kernel.org> # 3.17.x
> > Signed-off-by: Andreas Färber <afaerber@...e.de>
> > ---
> > Michal/Olof, please consider this trivial patch as a fix for 3.18.
>
> Acked-by: Michal Simek <michal.simek@...inx.com>
>
> Olof, Arnd: Can you please pick this directly?
Done, applied to fixes.
-Olof
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