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Open Source and information security mailing list archives
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Date: Mon, 17 Nov 2014 23:39:43 -0800 From: Yinghai Lu <yinghai@...nel.org> To: Kees Cook <keescook@...omium.org> Cc: Thomas Gleixner <tglx@...utronix.de>, Laura Abbott <lauraa@...eaurora.org>, Russell King <rmk+kernel@....linux.org.uk>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>, "the arch/x86 maintainers" <x86@...nel.org>, Andrew Morton <akpm@...ux-foundation.org>, Andy Lutomirski <luto@...capital.net>, Yasuaki Ishimatsu <isimatu.yasuaki@...fujitsu.com>, Wang Nan <wangnan0@...wei.com>, David Vrabel <david.vrabel@...rix.com> Subject: Re: [PATCH v2] x86, mm: set NX across entire PMD at boot On Mon, Nov 17, 2014 at 12:27 PM, Kees Cook <keescook@...omium.org> wrote: > On Sun, Nov 16, 2014 at 3:44 PM, Thomas Gleixner <tglx@...utronix.de> wrote: >> >> So the initial patch to get rid of the X mapping is of course to just >> extend the area to the PMD. A little bit different to your initial >> patch, but essentially the same. >> >> - unsigned long all_end = PFN_ALIGN(&_end); >> + unsigned long all_end = roundup((unsigned long) &_end, PMD_SIZE); >> >> I'm going to apply your V1 patch with the above roundup() >> simplification. If a page of that area gets used later on then we are >> going to split up the PMD anyway. > > That's fine by me. Yinghai Lu seems to have potentially better > solutions, but my head is spinning after reading more of this thread. > :) I just want to make sure that at the end of the day, there are no > RW+x mappings. > Please check v3 that cleanup highmap in the middle. Before patch: ---[ High Kernel Mapping ]--- 0xffffffff80000000-0xffffffff81000000 16M pmd 0xffffffff81000000-0xffffffff82200000 18M ro PSE GLB x pmd 0xffffffff82200000-0xffffffff82c00000 10M ro PSE GLB NX pmd 0xffffffff82c00000-0xffffffff82e00000 2M RW PSE GLB NX pmd 0xffffffff82e00000-0xffffffff83000000 2M RW GLB NX pte 0xffffffff83000000-0xffffffff83200000 2M RW PSE GLB NX pmd 0xffffffff83200000-0xffffffff83400000 2M RW GLB NX pte 0xffffffff83400000-0xffffffff84200000 14M RW PSE GLB NX pmd 0xffffffff84200000-0xffffffff843a2000 1672K RW GLB NX pte 0xffffffff843a2000-0xffffffff84400000 376K RW GLB x pte 0xffffffff84400000-0xffffffffa0000000 444M pmd After patch: ---[ High Kernel Mapping ]--- 0xffffffff80000000-0xffffffff81000000 16M pmd 0xffffffff81000000-0xffffffff82000000 16M ro PSE GLB x pmd 0xffffffff82000000-0xffffffff82011000 68K ro GLB x pte 0xffffffff82011000-0xffffffff82200000 1980K pte 0xffffffff82200000-0xffffffff82a00000 8M ro PSE GLB NX pmd 0xffffffff82a00000-0xffffffff82a1d000 116K ro GLB NX pte 0xffffffff82a1d000-0xffffffff82c00000 1932K pte 0xffffffff82c00000-0xffffffff82e00000 2M RW PSE GLB NX pmd 0xffffffff82e00000-0xffffffff82e52000 328K RW GLB NX pte 0xffffffff82e52000-0xffffffff83000000 1720K pte 0xffffffff83000000-0xffffffff83200000 2M pmd 0xffffffff83200000-0xffffffff83213000 76K pte 0xffffffff83213000-0xffffffff83400000 1972K RW GLB NX pte 0xffffffff83400000-0xffffffff84200000 14M RW PSE GLB NX pmd 0xffffffff84200000-0xffffffff84383000 1548K RW GLB NX pte 0xffffffff84383000-0xffffffff84400000 500K pte 0xffffffff84400000-0xffffffffa0000000 444M pmd Thanks Yinghai View attachment "nx_after_end_v3_1.patch" of type "text/x-patch" (3069 bytes) View attachment "nx_after_end_v3_2.patch" of type "text/x-patch" (6281 bytes)
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