linux-kernel - Re: [PATCH 1/2] clk: rockchip: add bindings for the mmc clock phases

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAD=FV=XL7hht32hu5zxXAJ+8BKbQp7aQOP68cCjKtrytGGs8iA@mail.gmail.com>
Date:	Tue, 18 Nov 2014 09:44:22 -0800
From:	Doug Anderson <dianders@...omium.org>
To:	Alexandru M Stan <amstan@...omium.org>
Cc:	Heiko Stuebner <heiko@...ech.de>, addy ke <addy.ke@...k-chips.com>,
	Sonny Rao <sonnyrao@...omium.org>,
	Kever Yang <kever.yang@...k-chips.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Mike Turquette <mturquette@...aro.org>,
	Mark yao <mark.yao@...k-chips.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] clk: rockchip: add bindings for the mmc clock phases

Hi,

On Fri, Nov 14, 2014 at 2:52 PM, Alexandru M Stan <amstan@...omium.org> wrote:
> This will be used in a later patch for clock phase tuning.
>
> Suggested-by: Heiko Stuebner <heiko@...ech.de>
> Signed-off-by: Alexandru M Stan <amstan@...omium.org>
> ---
>  include/dt-bindings/clock/rk3288-cru.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
> index 100a08c..465d0f6 100644
> --- a/include/dt-bindings/clock/rk3288-cru.h
> +++ b/include/dt-bindings/clock/rk3288-cru.h
> @@ -72,6 +72,16 @@
>  #define SCLK_HEVC_CABAC                111
>  #define SCLK_HEVC_CORE         112
>
> +#define SCLK_SDMMC_DRV_PHASE   113
> +#define SCLK_SDIO0_DRV_PHASE   114
> +#define SCLK_SDIO1_DRV_PHASE   115
> +#define SCLK_EMMC_DRV_PHASE    116
> +
> +#define SCLK_SDMMC_SAMPLE_PHASE        117
> +#define SCLK_SDIO0_SAMPLE_PHASE        118
> +#define SCLK_SDIO1_SAMPLE_PHASE        119
> +#define SCLK_EMMC_SAMPLE_PHASE 120
> +

Thinking about Mike T's comment, we might want to actually rename
these defines and just remove the "_PHASE".  These clocks _are_ the
drive and sample clocks.  Sure, they happen to have phases as one of
the attributes, but they aren't "phase clocks".

FYI, the TRM shows these clocks as:

- Into "clkgen" you see cclkin (the *2 clock)
- Out of "clkgen" you see:
  --> "cclk_in" (the non *2 clock)
  --> "cclk_in_drv" (the drive clock, which might be shifted)
  --> "cclk_in_sample" (the sample clock, which might be shifted)

Right now we're not modeling the non-shifted, non *2 clock.  I think
that's OK (otherwise we've got a bunch of old device trees to change,
since the old DTS files passed in the *2 clock as the card clock).


-Doug
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/