linux-kernel - [PATCH] clk: rockchip: fix rk3188 USB HSIC PHY clock divider

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Date:	Fri, 21 Nov 2014 11:08:47 +0100
From:	Julien CHAUVEAU <julien.chauveau@...-technologies.fr>
To:	Heiko Stuebner <heiko@...ech.de>,
	Mike Turquette <mturquette@...aro.org>,
	linux-arm-kernel@...ts.infradead.org (moderated list:ARM/Rockchip
	SoC...),
	linux-rockchip@...ts.infradead.org (open list:ARM/Rockchip SoC...),
	linux-kernel@...r.kernel.org (open list:COMMON CLK FRAMEWORK)
Cc:	Julien CHAUVEAU <julien.chauveau@...-technologies.fr>
Subject: [PATCH] clk: rockchip: fix rk3188 USB HSIC PHY clock divider

The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).

Signed-off-by: Julien CHAUVEAU <julien.chauveau@...-technologies.fr>
---
 drivers/clk/rockchip/clk-rk3188.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 725d841..f27ea47 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -664,7 +664,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
 			RK2928_CLKGATE_CON(3), 6, GFLAGS),
 	DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
-			RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
+			RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
 
 	MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
 			RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
-- 
2.1.0

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