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Message-ID: <alpine.DEB.2.11.1411232028250.6439@nanos>
Date: Sun, 23 Nov 2014 20:29:08 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: Matt Fleming <matt@...sole-pimps.org>
cc: Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel@...r.kernel.org, vikas.shivappa@...el.com,
hpa@...or.com, mingo@...nel.org, tj@...nel.org,
matt.fleming@...el.com, will.auld@...el.com, peterz@...radead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Sun, 23 Nov 2014, Matt Fleming wrote:
> Something like this?
>
> first_bit = find_next_bit(map, nr_bits, -1);
> zero_bit = find_next_zero_bit(map, nr_bits, first_bit);
>
> if (find_next_bit(map, nr_bits, zero_bit) < nr_bits)
> return -EINVAL; /* non-contiguous bits */
Looks pretty self explaining, right?
Thanks,
tglx
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