lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <201411281613.11626.arnd@arndb.de>
Date:	Fri, 28 Nov 2014 16:13:11 +0100
From:	Arnd Bergmann <arnd@...db.de>
To:	suravee.suthikulpanit@....com
Cc:	olof@...om.net, mark.rutland@....com, will.deacon@....com,
	marc.zyngier@....com, catalin.marinas@....com,
	robherring2@...il.com, liviu.dudau@....com,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	arm@...nel.org, Thomas Lendacky <Thomas.Lendacky@....com>,
	Joel Schopp <Joel.Schopp@....com>
Subject: Re: [PATCH V5] arm64: amd-seattle: Adding device tree for AMD Seattle platform

On Wednesday 26 November 2014, suravee.suthikulpanit@....com wrote:
> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
> 
> Initial revision of device tree for AMD Seattle Development platform.
> 
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Marc Zyngier <marc.zyngier@....com>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
> Signed-off-by: Thomas Lendacky <Thomas.Lendacky@....com>
> Signed-off-by: Joel Schopp <Joel.Schopp@....com>
> ---
> V5 Changes:
>   * Rebase to arm-soc for-next (per Olof)
>   * Restructure the DTS/DTSI into board and SoC configurations (per Olof)
>   * Add model property at the top level (per Olof)
>   * Move pcie0 under smb and change smb's ranges property to empty since pcie
>     is not in the same range. (per Olof)
>   * Change v2m0's ranges property (per Arnd)
>   * Change timer interrupt type to level-trigger (per Marc)

Applied to next/arm64, thanks!

Looking at this one more time, I had another question:

> +	smb0: smb {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* DDR range is 40-bit addressing */
> +		dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
> +

What is a DDR range?

Also, what is special about the last byte? Did you intentionally
leave it out? I think when we calculate the dma mask, we will
use 0x3fffffffff so we don't step on the last byte, which I assume
is not what you intended.

	Arnd
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ