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Message-ID: <54809C88.8060601@caviumnetworks.com>
Date: Thu, 4 Dec 2014 09:40:24 -0800
From: David Daney <ddaney@...iumnetworks.com>
To: "Maciej W. Rozycki" <macro@...ux-mips.org>
CC: Leonid Yegoshin <Leonid.Yegoshin@...tec.com>,
David Daney <ddaney.cavm@...il.com>,
<linux-mips@...ux-mips.org>, Ralf Baechle <ralf@...ux-mips.org>,
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<peterz@...radead.org>, <paul.gortmaker@...driver.com>,
<chenhc@...ote.com>, <cl@...ux.com>,
Ingo Molnar <mingo@...nel.org>, <richard@....at>,
<zajec5@...il.com>, <james.hogan@...tec.com>,
<keescook@...omium.org>, <tj@...nel.org>, <alex@...x-smith.me.uk>,
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<dengcheng.zhu@...tec.com>, <manuel.lauss@...il.com>,
<lars.persson@...s.com>, David Daney <david.daney@...ium.com>
Subject: Re: [PATCH 2/3] MIPS: Add full ISA emulator.
On 12/04/2014 03:49 AM, Maciej W. Rozycki wrote:
> On Wed, 3 Dec 2014, David Daney wrote:
>
>>> but it doesn't support customized instructions,
>>
>> GCC will never put these in the delay slot of a FPU branch, so it is not
>> needed.
>>
>>> multiple ASEs,
>>
>> Same as above. But any instructions that are deemed necessary can easily be
>> added.
>
> GAS will happily schedule any instruction into a branch delay slot as
> long as the instruction is not architecturally forbidden there (e.g.
> ERET), there is no data dependency with the branch that would affect the
> result produced and the instruction is not an explicit exception trap
> operation (BREAK, SYSCALL, TEQ, etc.). For some reason, unknown to me all
> MT ASE instructions are disallowed too. Anything else -- free to go in!
>
> Of course instructions can be scheduled into branch delay slots manually
> too, in handcoded assembly, and that has to continue working.
>
It is not difficult to also emulate the trapping instructions. In order
to move forward, I will implement the trapping instructions in my
emulator for the next patch.
Thanks,
David Daney
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