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Message-ID: <CAFcVECL0ShFp-qSHmO8era3okebA4oO85iz+QRWP6fKAEMiN7A@mail.gmail.com>
Date: Fri, 5 Dec 2014 09:42:30 +0530
From: Harini Katakam <harinikatakamlinux@...il.com>
To: Wolfram Sang <wsa@...-dreams.de>
Cc: Mark Rutland <mark.rutland@....com>,
Michal Simek <michal.simek@...inx.com>,
Sören Brinkmann <soren.brinkmann@...inx.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"vishnum@...inx.com" <vishnum@...inx.com>
Subject: Re: [PATCH v2 3/3] i2c: cadence: Check for errata condition involving
master receive
Hi,
On Fri, Dec 5, 2014 at 12:04 AM, Wolfram Sang <wsa@...-dreams.de> wrote:
>
>> + /*
>> + * This controller does not give completion interrupt after a
>> + * master receive transfer if HOLD bit is set (repeated start),
>> + * resulting in SW timeout. Hence, if a receive transfer is
>> + * followed by any other transfer, an error is returned
>> + * indicating that this sequence is not supported.
>> + */
>> + for (count = 0; count < num-1; count++) {
>> + if (msgs[count].flags & I2C_M_RD)
>> + return -EOPNOTSUPP;
>> + }
>
> Yeah, a lot better. Probably it would be good to inform the user with a
> warning what went wrong?
>
Sure. I'll add that.
Regards,
Harini
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