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Message-ID: <54827D3C.3080401@pobox.com>
Date:	Sat, 06 Dec 2014 12:51:24 +0900
From:	Shinya Kuribayashi <skuribay@...ox.com>
To:	david.e.box@...ux.intel.com, wsa@...-dreams.de
CC:	jdelvare@...e.de, arnd@...db.de, maxime.ripard@...e-electrons.com,
	dianders@...omium.org, u.kleine-koenig@...gutronix.de,
	laurent.pinchart+renesas@...asonboard.com,
	boris.brezillon@...e-electrons.com, andrew@...n.ch,
	sjg@...omium.org, markus.mayer@...aro.org,
	jacob.jun.pan@...ux.intel.com, max.schwarz@...ine.de,
	mika.westerberg@...ux.intel.com, Romain.Baeriswyl@...lis.com,
	wenkai.du@...el.com, chiau.ee.chew@...el.com, alan@...ux.intel.com,
	linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org
Subject: Re: [PATCH V3 0/2] i2c-designware: Baytrail bus locking driver

On 14/12/02 9:09, David E. Box wrote:
> Select Intel Baytrail platforms support PMIC's whose i2c bus may be controlled
> exclusively by platform hardware. This patch set adds support for i2c bus
> locking to the designware core and provides a driver module for managing
> the lock on these platforms. Since the lock on these systems isn't enumerable
> outside of the i2c platform driver, the locking functions are assigned at
> compile time.

Have you ever look into the hwspinlock framework?  It seems to me that
such an exclusive operation between CPUs and external hardware blocks
is exactly what hwspinlock is for.  Further more hwspinlock takes care
of exclusiveness between SMP cores.

Ideally I would expect i2c-designware to have hwspinlock lock/unlock
API calls on one I2C transaction, but it's not necessarily the case.
Introducing such platform hooks (acquire_lock and release_lock) and
keeping actual exclusive operataion outside the driver might be good
for various usecases/platforms.

   Shinya

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