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Message-ID: <20141224164600.GA20268@amd>
Date: Wed, 24 Dec 2014 17:46:00 +0100
From: Pavel Machek <pavel@....cz>
To: kernel list <linux-kernel@...r.kernel.org>, yoongukim@....edu,
donghyu1@....edu, omutlu@...il.com
Subject: Re: DRAM unreliable under specific access patern
Hi!
(I added original researches to the list).
I see you have FPGA-based detector, and probably PC based detector,
too. Would it be possible to share sources of the PC based one?
Thanks,
Pavel
On Wed 2014-12-24 17:38:23, Pavel Machek wrote:
> Hi!
>
> It seems that it is easy to induce DRAM bit errors by doing repeated
> reads from adjacent memory cells on common hw. Details are at
>
> https://www.ece.cmu.edu/~safari/pubs/kim-isca14.pdf
>
> . Older memory modules seem to work better, and ECC should detect
> this. Paper has inner loop that should trigger this.
>
> Workarounds seem to be at hardware level, and tricky, too.
>
> Does anyone have implementation of detector? Any ideas how to work
> around it in software?
>
> Pavel
--
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