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Date:	Wed, 24 Dec 2014 09:38:22 -0800
From:	Andy Lutomirski <>
To:	Pavel Machek <>
Cc:	kernel list <>
Subject: Re: DRAM unreliable under specific access patern

On Wed, Dec 24, 2014 at 9:25 AM, Pavel Machek <> wrote:
> On Wed 2014-12-24 09:13:32, Andy Lutomirski wrote:
>> On Wed, Dec 24, 2014 at 8:38 AM, Pavel Machek <> wrote:
>> > Hi!
>> >
>> > It seems that it is easy to induce DRAM bit errors by doing repeated
>> > reads from adjacent memory cells on common hw. Details are at
>> >
>> >
>> >
>> > . Older memory modules seem to work better, and ECC should detect
>> > this. Paper has inner loop that should trigger this.
>> >
>> > Workarounds seem to be at hardware level, and tricky, too.
>> One mostly-effective solution would be to stop buying computers
>> without ECC.  Unfortunately, no one seems to sell non-server chips
>> that can do ECC.
> Or keep using old computers :-).
>> > Does anyone have implementation of detector? Any ideas how to work
>> > around it in software?
>> >
>> Platform-dependent page coloring with very strict, and impossible to
>> implement fully correctly, page allocation constraints?
> This seems to be at cacheline level, not at page level, if I
> understand it correctly.
> So the problem would is: I have something mapped read-only, and I can
> still cause bitflips in it.
> Hmm. So it is pretty obviously a security problem, no need for
> java. Just do some bit flips in binary root is going to run, and it
> will crash for him. You can map binaries read-only, so you have enough
> access.

Right.  So we're mostly screwed.

> As far as I understand it, attached program could reproduce it on
> affected machines?

I thought that article suggested using addresses 8M (is that 8
megabytes?) apart for the two accesses.


>                                                                         Pavel
> --
> (english)
> (cesky, pictures)

Andy Lutomirski
AMA Capital Management, LLC
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