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Message-ID: <1419584751-18149-4-git-send-email-flora.fu@mediatek.com>
Date: Fri, 26 Dec 2014 17:05:51 +0800
From: Flora Fu <flora.fu@...iatek.com>
To: Philipp Zabel <p.zabel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Russell King <linux@....linux.org.uk>,
Grant Likely <grant.likely@...aro.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<srv_heupstream@...iatek.com>,
Sascha Hauer <kernel@...gutronix.de>,
Olof Johansson <olof@...om.net>, Arnd Bergmann <arnd@...db.de>,
Flora Fu <flora.fu@...iatek.com>,
Eddie Huang <eddie.huang@...iatek.com>,
Yingjoe Chen <yingjoe.chen@...iatek.com>,
Dongdong Cheng <dongdong.cheng@...iatek.com>,
HenryC Chen <henryc.chen@...iatek.com>,
Menghui Lin <menghui.lin@...iatek.com>,
Chen Zhong <chen.zhong@...iatek.com>
Subject: [PATCH v4 3/3] arm: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135.dtsi.
Acked-by: Philipp Zabel <p.zabel@...gutronix.de>
Signed-off-by: Flora Fu <flora.fu@...iatek.com>
---
arch/arm/boot/dts/mt8135.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index ec83e69..989e488 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset-controller/mt8135-resets.h>
#include "skeleton64.dtsi"
/ {
@@ -100,6 +101,34 @@
compatible = "simple-bus";
ranges;
+ infracfg: syscon@...01000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset", "mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+ };
+
+ pericfg: syscon@...03000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+
+ perirst: reset-controller@00 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg-reset", "mediatek,reset";
+ reg = <0x00 0x8>;
+ };
+ };
+
timer: timer@...08000 {
compatible = "mediatek,mt8135-timer",
"mediatek,mt6577-timer";
--
1.8.1.1.dirty
--
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