linux-kernel - Re: [PATCH v2 5/5] KVM: nVMX: Enable nested posted interrupt processing.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CACzj_yWDkuNxu=-Fqy3aPJJ_sveeCtmjKJRAvEjsNb+-7kdjAQ@mail.gmail.com>
Date:	Wed, 21 Jan 2015 16:44:03 +0800
From:	Wincy Van <fanwenyi0529@...il.com>
To:	"Zhang, Yang Z" <yang.z.zhang@...el.com>
Cc:	Paolo Bonzini <pbonzini@...hat.com>,
	"gleb@...nel.org" <gleb@...nel.org>,
	"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Wanpeng Li <wanpeng.li@...ux.intel.com>,
	Jan Kiszka <jan.kiszka@....de>
Subject: Re: [PATCH v2 5/5] KVM: nVMX: Enable nested posted interrupt processing.

On Wed, Jan 21, 2015 at 4:07 PM, Zhang, Yang Z <yang.z.zhang@...el.com> wrote:
>> +       if (vector == vmcs12->posted_intr_nv &&
>> +           nested_cpu_has_posted_intr(vmcs12)) {
>> +               if (vcpu->mode == IN_GUEST_MODE)
>> +                       apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
>> +                               POSTED_INTR_VECTOR);
>> +               else {
>> +                       r = -1;
>> +                       goto out;
>> +               }
>> +
>> +               /*
>> +                * if posted intr is done by hardware, the
>> +                * corresponding eoi was sent to L0. Thus
>> +                * we should send eoi to L1 manually.
>> +                */
>> +               kvm_apic_set_eoi_accelerated(vcpu,
>> +                       vmcs12->posted_intr_nv);
>
> Why this is necessary? As your comments mentioned, it is done by hardware not L1, why L1 should aware of it?
>

According to SDM 29.6, if the processor recognizes a posted interrupt,
it will send an EOI to LAPIC.
If the posted intr is done by hardware, the processor will send eoi to
hardware LAPIC, not L1's, just
like the none-nested case(the physical interrupt is dismissed). So we
should take care of the L1's
LAPIC and send an eoi to it.


Thanks,

Wincy
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/