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Message-ID: <20150122074001.GB427@ulmo>
Date: Thu, 22 Jan 2015 08:40:02 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Dmitry Osipenko <digetx@...il.com>
Cc: Wolfram Sang <wsa@...-dreams.de>,
Stephen Warren <swarren@...dotorg.org>,
Alexandre Courbot <gnurou@...il.com>,
Laxman Dewangan <ldewangan@...dia.com>,
Ben Dooks <ben.dooks@...ethink.co.uk>,
Bob Mottram <bob.mottram@...ethink.co.uk>,
linux-tegra@...r.kernel.org, linux-i2c@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] i2c: tegra: Maintain CPU endianness
On Tue, Jan 20, 2015 at 03:22:25PM +0300, Dmitry Osipenko wrote:
> Support CPU BE mode by adding endianness conversion for memcpy interactions.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> drivers/i2c/busses/i2c-tegra.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 28b87e6..e0d3ef1 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -286,6 +286,7 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
> if (rx_fifo_avail > 0 && buf_remaining > 0) {
> BUG_ON(buf_remaining > 3);
> val = i2c_readl(i2c_dev, I2C_RX_FIFO);
> + val = cpu_to_le32(val);
Should this not technically be le32_to_cpu() since the data originates
from the I2C controller?
> memcpy(buf, &val, buf_remaining);
> buf_remaining = 0;
> rx_fifo_avail--;
> @@ -343,7 +344,9 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
> */
> if (tx_fifo_avail > 0 && buf_remaining > 0) {
> BUG_ON(buf_remaining > 3);
> + val = 0;
Why does this have to be initialized to 0 now?
Thierry
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