linux-kernel - Re: [PATCH 6/8] usb: dwc3: add ULPI interface support

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Date:	Fri, 13 Feb 2015 16:04:56 -0600
From:	Felipe Balbi <balbi@...com>
To:	David Cohen <david.a.cohen@...ux.intel.com>
CC:	Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
	Felipe Balbi <balbi@...com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Baolu Lu <baolu.lu@...ux.intel.com>,
	<linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 6/8] usb: dwc3: add ULPI interface support

On Fri, Feb 13, 2015 at 02:03:45PM -0800, David Cohen wrote:
> Hi Heikki,
> 
> On Fri, Feb 13, 2015 at 03:16:40PM +0200, Heikki Krogerus wrote:
> > On Thu, Feb 12, 2015 at 05:41:30PM -0800, David Cohen wrote:
> > > On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote:
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index a8c9062..66cbf38 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > > > > >  	platform_set_drvdata(pdev, dwc);
> > > > > >  	dwc3_cache_hwparams(dwc);
> > > > > >  
> > > > > > +	ret = dwc3_ulpi_init(dwc);
> > > > > 
> > > > > If I understood correctly, this call will result in enumerating the phy
> > > > > via ULPI bus, then registering the correct ULPI device.
> > > > > Can you guarantee ULPI will be always accessible at this point if we
> > > > > remove dwc3 module and load it again?
> > > > 
> > > > OK, got it. So yes, I can guarantee that ULPI will be acessible at
> > > > this point. If we are in a state where we could soft reset dwc3, we
> > > > know we can access ULPI. The fact that dwc3 itself expects to be able
> > > > to write to the ULPI registers at that point guarantees it for us.
> > > 
> > > I just double checked DWC3 TRM.
> > > You are correct, by the time we're executing dwc3_core_soft_reset() ULPI
> > > bus is already accessible. But the TRM also specifies an ULPI phy would
> > > be reset by DCTL's core soft reset, which is executed by dwc3_core_init()
> > > before calling dwc3_core_soft_reset(). It does mention DWC3 writes data
> > > to an ULPI phy register during reset, but it also mentions the clock
> > > sync happens during that time.
> > > 
> > > That makes no even OK, but more correct IMO to power on phy before
> > > core's soft reset (i.e. by ACPI methods). But it lets us in a grey area
> > > whether ULPI is reliably accessible before core's soft reset.
> > > 
> > > I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after
> > > core's soft reset we've got no more grey area.
> > 
> > Well, we have already requested the phys in dwc3_probe before that so
> > some refactoring will be needed. It's probable no a problem.
> 
> Sounds good :)
> 
> > 
> > Btw, I'm sorry about telling this so late, but I'm going to be on
> > vacation for the next two weeks.
> 
> Thanks for the notice.

you'll be back right around merge window closing time :-) Not to worry,
we'll have time to get this into the next merge window.

-- 
balbi

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