linux-kernel - [PATCH] clk: qcom: fix RCG M/N counter configuration

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Message-Id: <1425462575-11486-1-git-send-email-architt@codeaurora.org>
Date:	Wed,  4 Mar 2015 15:19:35 +0530
From:	Archit Taneja <architt@...eaurora.org>
To:	sboyd@...eaurora.org
Cc:	mturquette@...aro.org, linux-arm-msm@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Archit Taneja <architt@...eaurora.org>
Subject: [PATCH] clk: qcom: fix RCG M/N counter configuration

Currently, a RCG's M/N counter (used for fraction division) is set to either
'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether
the corresponding rcg struct has a mnd field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is still enabled
by code even though no division takes place. Leaving the RCG in such a state
can result in improper behavior. This was observed with the DSI pixel clock RCG
when M and N were both set to 1.

Add an additional check (M != N) to enable the M/N counter only when it's needed
for fraction division.

Signed-off-by: Archit Taneja <architt@...eaurora.org>
---
 drivers/clk/qcom/clk-rcg2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 08b8b37..4fe9c01 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -242,7 +242,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 	mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
 	cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
 	cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
-	if (rcg->mnd_width && f->n)
+	if (rcg->mnd_width && f->n && (f->m != f->n))
 		cfg |= CFG_MODE_DUAL_EDGE;
 	ret = regmap_update_bits(rcg->clkr.regmap,
 			rcg->cmd_rcgr + CFG_REG, mask, cfg);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

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