linux-kernel - Re: [PATCH v6 03/15] soc/tegra: Add ram code reader helper

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Date:	Mon, 9 Mar 2015 15:36:54 +0100
From:	Tomeu Vizoso <tomeu.vizoso@...labora.com>
To:	Mikko Perttunen <mikko.perttunen@...si.fi>
Cc:	Alexandre Courbot <gnurou@...il.com>,
	"linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
	Javier Martinez Canillas <javier.martinez@...labora.co.uk>,
	Mikko Perttunen <mperttunen@...dia.com>,
	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Peter De Schrijver <pdeschrijver@...dia.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 03/15] soc/tegra: Add ram code reader helper

On 2 March 2015 at 10:52, Mikko Perttunen <mikko.perttunen@...si.fi> wrote:
> On 03/02/2015 10:46 AM, Alexandre Courbot wrote:
>>
>> On Thu, Feb 12, 2015 at 11:06 PM, Tomeu Vizoso
>> <tomeu.vizoso@...labora.com> wrote:
>>>
>>> From: Mikko Perttunen <mperttunen@...dia.com>
>>>
>>> Needed for the EMC and MC drivers to know what timings from the DT to
>>> use.
>>>
>>> Signed-off-by: Mikko Perttunen <mperttunen@...dia.com>
>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@...labora.com>
>>>
>>> ---
>>>
>>> v4: Replace magic number with PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT
>>> ---
>>>   drivers/soc/tegra/fuse/tegra-apbmisc.c | 19 +++++++++++++++++++
>>>   include/soc/tegra/fuse.h               |  1 +
>>>   2 files changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c
>>> b/drivers/soc/tegra/fuse/tegra-apbmisc.c
>>> index 3bf5aba..dc96a62 100644
>>> --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
>>> +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
>>> @@ -28,8 +28,13 @@
>>>   #define APBMISC_SIZE   0x64
>>>   #define FUSE_SKU_INFO  0x10
>>>
>>> +#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT     4
>>> +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG (0xf <<
>>> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
>>> +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT        (0x3 <<
>>> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
>>
>>
>> I think you are slightly over 80 chars here.
>>
>>> +
>>>   static void __iomem *apbmisc_base;
>>>   static void __iomem *strapping_base;
>>> +static bool          long_ram_code;
>>>
>>>   u32 tegra_read_chipid(void)
>>>   {
>>> @@ -54,6 +59,18 @@ u32 tegra_read_straps(void)
>>>                  return 0;
>>>   }
>>>
>>> +u32 tegra_read_ram_code(void)
>>> +{
>>> +       u32 straps = tegra_read_straps();
>>> +
>>> +       if (long_ram_code)
>>> +               straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
>>> +       else
>>> +               straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
>>> +
>>> +       return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
>>> +}
>>> +
>>>   static const struct of_device_id apbmisc_match[] __initconst = {
>>>          { .compatible = "nvidia,tegra20-apbmisc", },
>>>          {},
>>> @@ -112,4 +129,6 @@ void __init tegra_init_apbmisc(void)
>>>          strapping_base = of_iomap(np, 1);
>>>          if (!strapping_base)
>>>                  pr_err("ioremap tegra strapping_base failed\n");
>>> +
>>> +       long_ram_code = of_property_read_bool(np,
>>> "nvidia,long-ram-code");
>>
>>
>> Is this long-ram property chip-dependent? If so, couldn't we just use
>> the chip ID or matched compatible string to decide whether the RAM
>> code length, instead of having a dedicated property for it?
>>
>
> I am under the impression that it is board-specific.

Yeah, some boards with the K1 will use only 2 bits for the ram-code
and others (notably the nyan chromebooks) will use 4.

Regards,

Tomeu

> Mikko
>
>
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