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Message-ID: <54FFFCC7.5090707@imgtec.com>
Date: Wed, 11 Mar 2015 08:28:55 +0000
From: Markos Chandras <Markos.Chandras@...tec.com>
To: David Daney <ddaney.cavm@...il.com>, <linux-mips@...ux-mips.org>,
<ralf@...ux-mips.org>
CC: <linux-kernel@...r.kernel.org>,
Leonid Yegoshin <Leonid.Yegoshin@...tec.com>,
David Daney <david.daney@...ium.com>
Subject: Re: [PATCH] Revert "MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard
for the EHB instruction"
On 02/23/2015 10:52 PM, David Daney wrote:
> From: David Daney <david.daney@...ium.com>
>
> This reverts commit 77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed.
>
> There are two problems:
>
> 1) It breaks OCTEON, which will now crash in early boot with:
>
> Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
>
> 2) The logic is broken.
>
> The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction
> is required. The offending patch attempts (and fails) to change the
> meaning to be that EHB is part of the ISA.
>
> Signed-off-by: David Daney <david.daney@...ium.com>
> ---
Hi,
First of all sorry about the octeon breakage.
However, whilst this patch will fix Octeon it will break R6
Can we please consider another patch that will simply use
cpu_has_mips_r2_r6 instead of cpu_has_mips_r2 so both will work in 4.0?
--
markos
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