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Message-ID: <20150319155253.GA30732@dtor-ws>
Date:	Thu, 19 Mar 2015 08:52:53 -0700
From:	Dmitry Torokhov <dmitry.torokhov@...il.com>
To:	Borislav Petkov <bp@...en8.de>
Cc:	Tejun Heo <tj@...nel.org>,
	Doug Thompson <dougthompson@...ssion.com>,
	linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org,
	Mauro Carvalho Chehab <mchehab@....samsung.com>,
	Tetsuo Handa <penguin-kernel@...ove.SAKURA.ne.jp>,
	Olof Johansson <olof@...om.net>,
	Arjan van de Ven <arjan@...ux.intel.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	"Luis R . Rodriguez" <mcgrof@...e.com>
Subject: Re: [PATCH 3/3] EDAC: amd64_edac: decide if driver can load
 successfully early.

On Thu, Mar 19, 2015 at 04:35:06PM +0100, Borislav Petkov wrote:
> On Thu, Mar 19, 2015 at 11:29:57AM -0400, Tejun Heo wrote:
> > This is a gloss layering violation.  Please don't do things like this.
> > I'm all for ripping out the hack even w/o considering the async probe
> > issue.
> 
> And I don't want to leave the driver loaded when there's nothing to
> be loaded for. One instance in this driver's specific case is one
> northbridge and there are numascale boxes with hundreds of northbridges.

Why does the number of bridges matter? Yo can have bazillion bridges, it
doe snot mean you'll have more than one copy of driver code. Note that
even with the changes we do not leave the driver bound to the devices if
there is no ECC.

> 
> If you have a better idea about how to unload the driver, asynchronously
> or not, after all probe() calls have failed, I'm all ears.

Given that PCI is hot pluggable you can never know when PCI done
enumerating (in  a broad sense).

Thanks.

-- 
Dmitry
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