linux-kernel - Re: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

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Date:	Thu, 2 Apr 2015 12:45:55 -0700
From:	Andi Kleen <ak@...ux.intel.com>
To:	kan.liang@...el.com
Cc:	a.p.zijlstra@...llo.nl, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/1] perf/x86/intel: Broadwell support LBR callstack

On Thu, Apr 02, 2015 at 04:12:57AM -0400, kan.liang@...el.com wrote:
> From: Kan Liang <kan.liang@...el.com>
> 
> Same as Haswell, Broadwell also support LBR callstack.
> 
> Signed-off-by: Kan Liang <kan.liang@...el.com>

Thanks looks good.

Acked-by: Andi Kleen <ak@...ux.intel.com>

-Andi


> ---
>  arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index fc6dbc4..4b61fe9 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2787,7 +2787,7 @@ __init int intel_pmu_init(void)
>  		hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
>  									      BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
>  
> -		intel_pmu_lbr_init_snb();
> +		intel_pmu_lbr_init_hsw();
>  
>  		x86_pmu.event_constraints = intel_bdw_event_constraints;
>  		x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
> -- 
> 1.8.3.1
> 

-- 
ak@...ux.intel.com -- Speaking for myself only
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