linux-kernel - Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMzpN2iZqJupeh+Woizxjmu4Xgn+G-equ-QfHwjeAZ1J7LgEAg@mail.gmail.com>
Date:	Wed, 1 Apr 2015 20:32:03 -0400
From:	Brian Gerst <brgerst@...il.com>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
Cc:	Denys Vlasenko <dvlasenk@...hat.com>,
	Ingo Molnar <mingo@...nel.org>,
	Steven Rostedt <rostedt@...dmis.org>,
	Borislav Petkov <bp@...en8.de>,
	"H. Peter Anvin" <hpa@...or.com>,
	Andy Lutomirski <luto@...capital.net>,
	Oleg Nesterov <oleg@...hat.com>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Alexei Starovoitov <ast@...mgrid.com>,
	Will Drewry <wad@...omium.org>,
	Kees Cook <keescook@...omium.org>,
	"the arch/x86 maintainers" <x86@...nel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions

On Wed, Apr 1, 2015 at 6:14 PM, Linus Torvalds
<torvalds@...ux-foundation.org> wrote:
> On Wed, Apr 1, 2015 at 1:52 PM, Denys Vlasenko <dvlasenk@...hat.com> wrote:
>>
>> BTW, AMD64 docs do explicitly say that MOVs from segment registers
>> to gpregs are zero-extending.
>
> Yeah, I think anything even *remotely* recent enough to do 64-bit does
> zero-extending.
>
> Even on the 32-bit side, anything that does register renaming is much
> better off with zero-extension than with partial register writes.
>
> And I found the "push" thing. It's actually documented:
>
>   "When pushing a segment selector onto the stack, the Pentium 4,
> Intel Xeon, P6 family, and Intel486 processors
> decrement the ESP register by the operand size and then write 2 bytes.
> If the operand size is 32-bits, the upper
> two bytes of the write are not modified"
>
> but I can't find any similar documentation for the "mov
> Sreg->register" thing. So now I'm starting to doubt my own memory.
>
>                           Linus

It's in the description of MOV:

"When the processor executes the instruction with a 32-bit
general-purpose register, it assumes that the 16 least-significant
bits of the general-purpose register are the destination or source
operand.  If the register is a destination operand, the resulting
value in the two high-order bytes of the register is implementation
dependent. For the Pentium 4, Intel Xeon, and P6 family processors,
the two high-order bytes are filled with zeros; for earlier 32-bit
IA-32 processors, the two high order bytes are undefined."

AMD will always zero-extend, although this applies specifically to
64-bit processors:

"When reading segment-registers with a 32-bit operand size, the
processor zero-extends the 16-bit selector results to 32 bits. When
reading segment-registers with a 64-bit operand size, the processor
zero-extends the 16-bit selector to 64 bits."

So I think it's safe to assume zero-extension on 64-bit, but not 32-bit.

--
Brian Gerst
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/