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Message-Id: <1428093571-20407-1-git-send-email-aaron.brice@datasoft.com>
Date: Fri, 3 Apr 2015 13:39:28 -0700
From: Aaron Brice <aaron.brice@...asoft.com>
To: broonie@...nel.org
Cc: linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org,
stefan@...er.ch, devicetree@...r.kernel.org
Subject: [PATCH v3 0/3] spi: fsl-dspi (vf610) clock fixes
We were having intermittent problems writing to SRAM chip on SPI bus on vf610
SoM. Added support for CS setup and hold times to meet the SRAM spec. In the
process noticed that the baud rate was a little high.
Changes since v2:
* Incorporate fixes per Stefen Agner review, namely moved hard-coded 50ns
delays to device tree properties
* Fix for baud rate scale value remainders, reported by Andy Shevchenko
Changes since v1:
* More detail in commit message for clock rate fix
Aaron Brice (3):
spi: fsl-dspi: Fix clock rate scale values
devicetree: spi: fsl-dspi: Add cs-sck delays
spi: fsl-dspi: Add ~50ns delay between cs and sck
.../devicetree/bindings/spi/spi-fsl-dspi.txt | 8 ++
drivers/spi/spi-fsl-dspi.c | 97 ++++++++++++++++++----
2 files changed, 89 insertions(+), 16 deletions(-)
--
2.1.0
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