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Message-ID: <20150407111934.GK6023@sirena.org.uk>
Date:	Tue, 7 Apr 2015 12:19:34 +0100
From:	Mark Brown <broonie@...nel.org>
To:	Andrew Bresticker <abrestic@...omium.org>
Cc:	linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/5] spi: img-spfi: Limit bit clock to 1/4th of input
 clock

On Mon, Apr 06, 2015 at 02:29:03PM -0700, Andrew Bresticker wrote:
> Although the SPFI BITCLK divider supports a value of up to 255, only
> values up to 128 are usable.  This results in a maximum possible bit
> clock rate of 1/4th the input clock rate.

Applied, thanks.

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