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Message-ID: <CACRpkdaoidr5RJs6d+4Vxtc9HXw6HOXsfQkqkui0h6za0_BQZA@mail.gmail.com>
Date: Wed, 8 Apr 2015 16:52:53 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
Mathias Nyman <mathias.nyman@...ux.intel.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>
Subject: Re: [PATCH] pinctrl: intel: Add Intel Sunrisepoint pin controller and
GPIO support
On Tue, Apr 7, 2015 at 3:42 PM, Mika Westerberg
<mika.westerberg@...ux.intel.com> wrote:
> We are going to use the same core for newer hardware as much as
> possible. Hopefully all new SoCs will have GPIO controller which is
> based on the same hardware design.
>
> For the existing, unfortunately the hardware differentiates too much
> from Sunrisepoint that it does not make much sense to factor them to use
> this new core.
OK fine. I was going to enquire into the similarity of this embedded Intel
HW IP to the old StrongARM, Xscale, and PXA or whatever other
embedded Intel things that have been around for ages, sometimes IP
is inherited in the strangest ways. Oh well I guess we might see if we
look at the register maps a bit.
Yours,
Linus Walleij
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