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Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077017C733A@SHSMSX103.ccr.corp.intel.com>
Date:	Wed, 15 Apr 2015 18:35:48 +0000
From:	"Liang, Kan" <kan.liang@...el.com>
To:	Peter Zijlstra <peterz@...radead.org>
CC:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"mingo@...nel.org" <mingo@...nel.org>,
	"acme@...radead.org" <acme@...radead.org>,
	"eranian@...gle.com" <eranian@...gle.com>,
	"andi@...stfloor.org" <andi@...stfloor.org>
Subject: RE: [PATCH V6 3/6] perf, x86: large PEBS interrupt threshold


> 
> On Thu, Apr 09, 2015 at 12:37:43PM -0400, Kan Liang wrote:
> > @@ -280,8 +280,9 @@ static int alloc_pebs_buffer(int cpu)
> >  	ds->pebs_absolute_maximum = ds->pebs_buffer_base +
> >  		max * x86_pmu.pebs_record_size;
> >
> > -	ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
> > -		thresh * x86_pmu.pebs_record_size;
> > +	if (x86_pmu.intel_cap.pebs_format < 1)
> > +		ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
> > +			x86_pmu.pebs_record_size;
> >
> >  	return 0;
> >  }
> 
> I can't seem to figure out what this is about.. help?

We move AUTO_RELOAD and large PEBS check to intel_pmu_hw_config.
But for earlier platform, it calls x86_pmu_hw_config.
So we force single PEBS record for old platform.

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