linux-kernel - Re: [PATCH v1] watchdog: Use a reference cycle counter to avoid scaling issues

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Date:	Fri, 24 Apr 2015 11:48:46 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
cc:	Andi Kleen <ak@...ux.intel.com>, Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
	Don Zickus <dzickus@...hat.com>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Anton Blanchard <anton@...ba.org>,
	Michael Ellerman <mpe@...erman.id.au>,
	linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH v1] watchdog: Use a reference cycle counter to avoid
 scaling issues

On Fri, 24 Apr 2015, Alexander Shishkin wrote:
> Thomas Gleixner <tglx@...utronix.de> writes:
> 
> > On Fri, 24 Apr 2015, Thomas Gleixner wrote:
> >> On Thu, 23 Apr 2015, Andi Kleen wrote:
> >> > > We can just detect the deviation in the callback itself:
> >> > > 
> >> > >        u64 now = ktime_get_mono_fast_ns();
> >> > > 
> >> > >        if (now - __this_cpu_read(nmi_timestamp) < period)
> >> > >        	       return;
> >> > > 
> >> > >        __this_cpu_write(nmi_timestamp, now);
> >> > > 
> >> > > It's that simple.
> >> > 
> >> > It's a simple short term hac^wsolution.
> >> 
> >> Yes, and way simpler and less complex for pushing into stable.
> >> 
> >> > But if we had a (hypothetical) system with let's say 10*TSC max you
> >> > may end up with quite a few false ticks, as in unnecessary
> >> > interrupts. With 100*TSC it would be really bad.
> >> 
> >> And hypothetical systems with 100*TSC justify all that?
> >>  
> >> > There were systems in the past that ran TSC at a much slower frequency,
> >> > such as the early AMD Barcelona systems.
> >> > 
> >> > So the problem may eventually come back if not solved properly.
> >> 
> >> There are better ways to do that than using heuristics. We have to
> >> deal with 3 variants of the reference counter:
> >> 
> >> 1) Core and Atom: counts bus cycles and we know that frequency already
> >>    	    	  from the local apic calibration
> >> 
> >> 2) Nehalem, Westmere: Same as TSC
> >> 
> >> 3) Sandybridge and later:  XCLK which is 100MHz
> >> 
> >> No magic calibration, just use the information which we have on our
> >> hands already.
> >
> > And aside of that calibration stuff emits a warning on everything
> > except intel, arc and metag. Very useful.
> >
> > This is core code and not intel playground.
> 
> This warning is only ever compiled on intel

Which means that all AMD machines will emit it.

Thanks,

	tglx
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