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Message-ID: <20150428134833.GJ1534@lahna.fi.intel.com>
Date: Tue, 28 Apr 2015 16:48:33 +0300
From: Mika Westerberg <mika.westerberg@...ux.intel.com>
To: Lee Jones <lee.jones@...aro.org>
Cc: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-kernel@...r.kernel.org,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
Jarkko Nikula <jarkko.nikula@...ux.intel.com>
Subject: Re: [PATCH v1 3/3] mfd: Add support for Intel Sunrisepoint LPSS
devices
On Tue, Apr 28, 2015 at 02:32:59PM +0100, Lee Jones wrote:
> On Tue, 31 Mar 2015, Andy Shevchenko wrote:
>
> > The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH.
> > The main difference to the previous platforms is that the LPSS devices are
> > compound devices where usually main (SPI, HSUART, or I2C) and DMA IPs are
> > present.
> >
> > This patch brings the driver for such devices found on Sunrisepoint PCH.
>
> I'm not convinced it's really an MFD. What does this hardware look
> like? Are the Designware devices really in the same memory/register
> space as the LPSS registers?
Yes they are - there is only single MMIO BAR per PCI device holding, the
host controller, iDMA and convergence layer registers.
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