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Message-ID: <55407D5F.20207@linux.intel.com>
Date: Wed, 29 Apr 2015 09:42:39 +0300
From: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
To: Lee Jones <lee.jones@...aro.org>,
Mika Westerberg <mika.westerberg@...ux.intel.com>
CC: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-kernel@...r.kernel.org,
Heikki Krogerus <heikki.krogerus@...ux.intel.com>
Subject: Re: [PATCH v1 3/3] mfd: Add support for Intel Sunrisepoint LPSS devices
Hi
On 04/28/2015 08:57 PM, Lee Jones wrote:
> On Tue, 28 Apr 2015, Mika Westerberg wrote:
>> On Tue, Apr 28, 2015 at 02:32:59PM +0100, Lee Jones wrote:
>>> I'm not convinced it's really an MFD. What does this hardware look
>>> like? Are the Designware devices really in the same memory/register
>>> space as the LPSS registers?
>>
>> Yes they are - there is only single MMIO BAR per PCI device holding, the
>> host controller, iDMA and convergence layer registers.
>
> Are there publicly available docs?
>
https://download.01.org/future-platform-configuration-hub/skylake/register-definitions/332219_001_Final.pdf
For instance UART Memory Mapped Registers (Chapter 1.2) starts from UART
MMIO BAR + offset 0 (LPSS_DEV_OFFSET in the patch), UART Additional
Registers (Ch 1.3) from offset 0x200 (LPSS_PRIV_OFFSET) and UART DMA
Controller Register (Ch 1.4) from offset 0x800 (LPSS_IDMA_OFFSET).
Idea here is that MFD layer here takes case of reset and clock control
as well as register the host controllers and integrated DMAs as platform
devices (not all have the iDMA and thus conditional registering of it
using the intel_lpss_has_idma()).
That allow us to keep this MFD part, host controller drivers and
drivers/dma/dw/ changes independent from each other. Fox example host
controller driver can detect the iDMA by checking is there a "lpss_priv"
resource and set the slave DMA parameters and DMA filter function
accordingly (which picks the channel only from associated iDMA device).
--
Jarkko
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